/*---Ctrl Bus---*/
    /*ALU ctrl*/
    `define ALU_OPI_BUS      4:0
    /*Forward ctrl*/
    `define FWD_SEL_BUS      1:0
    /*GENAral ctrl*/
    `define CTRL_IO_BUS      5:0		    
    /*Flush ctrl*/
    `define FLU_BUS          4:0
/*---Data---*/
	/*Inst path*/
	`define INST_BUS        31:0
    /*Data path*/
	`define REGD_BUS        63:0
    
	`define REGW_BUS        31:0
	`define REGH_BUS        15:0
	`define SHIF_BUS         4:0

	`define IMMD_BUS        63:0
	`define IMMW_BUS        31:0
	`define IMMH_BUS        15:0

	`define CSRI_BUS        63:0
	
	`define ALUD_BUS        63:0
	`define ALUW_BUS        31:0
	`define ALUH_BUS        15:0
	
	`define MEMD_BUS        63:0
	`define MEMW_BUS        31:0
	`define MEMH_BUS        15:0
	
	/*PC path*/
	`define PCIO_WIDIH	    63:0
	`define PC_INCREI      64'd0    
/*---Addr---*/
	/*Mem addr*/
	`define	IMEM_ADDR_BUS   19:0 
	`define	DMEM_ADDR_BUS   19:0
	/*General reg files addr */
	`define   GRF_ADDR_BUS   4:0
	/*Control state reg addr*/
	`define   CSR_ADDR_BUS  11:0
	/*GPIO peripheral addr*/
	`define   PPH_ADDR_BUS 
    
/*---Instr zero---*/
	`define  INSTR_ZERO  32'd0
/*---Data  zero---*/
	`define   REGD_ZERO  64'd0
	`define   IMMD_ZERO  64'd0
	`define     PC_ZERO  64'd0
	`define   ALUD_ZERO  64'd0
	`define	  CSRD_ZERO  64'd0
/*---Ctrl zero---*/
	`define	   RST_ENA   1'b0 //low ENA
	`define    GEN_DIS   1'b0
	`define    CTR_DIS   6'd0
	`define    STL_DIS   5'd0
    `define   LOAD_DIS   3'd0
	`define    MWR_DIS   1'b0
	`define    MRE_DIS   1'b0
	`define    BRA_DIS   1'b0
	`define   INST_DIS	 1'b0	
/*---Addr zero & begin---*/
	`define REG_FILE_0   5'd0
	`define INST_A_STA  20'd0
	`define DATA_A_STA  20'd0
	`define CSRT_A_STA  20'd0
/*--logic zero---*/
	`define LOGI_FALSE   1'b0

/*--Ctrl set---*/
	 `define 	RST_DIS   1'b1
	 `define	GEN_ENA	  1'b1
	 `define    MWR_ENA   1'b1
	 `define    MRE_ENA   1'b1
	 `define    BRA_ENA   1'b1
	 `define    STL_BAJ   5'hf
	 `define   INST_ENA	  1'b1
	 `define    IMM_SEL   1'b1
/*--Data set---*/
     `define    REG_SET  32'b1
/*---Logic True---*/
	 `define  LOGI_TRUE   1'b1
/*---Addr set---*/
	 `define  PC_REBOOT 64'h80

    `define INST_RV32I_OPCODE_NOP     7'b0000000
    `define INST_RV32I_OPCODE_LUI     7'b0110111 // {imm[31:12],             rd,             opcode=0110111}
    `define INST_RV32I_OPCODE_AUIPC   7'b0010111 // {imm[31:12],             rd,             opcode=0010111}
    `define INST_RV32I_OPCODE_JAL     7'b1101111 // {imm[20|10:1|11|19:12],  rd,             opcode=1101111}
    `define INST_RV32I_OPCODE_JALR    7'b1100111 // {imm[11:0],  rs1, 000,   rd,             opcode=1100111}
    `define INST_RV32I_OPCODE_BRANCH  7'b1100011// {imm[12|10:5],rs2,rs1,funct3,imm[4:1|11], opcode=1100011}
    `define INST_RV32DI_OPCODE_LOAD   7'b0000011 // {imm[11:0],  rs1, funct3,rd,             opcode=0000011}
    `define INST_RV32DI_OPCODE_STORE  7'b0100011 // {imm[11:5],  rs2, rs1,funct3,imm[4:0],   opcode=0100011}
    `define INST_RV32I_OPCODE_IMM     7'b0010011 // {imm[11:0],  rs1, funct3,rd,             opcode=0010011}
    `define INST_RV32I_OPCODE_REG     7'b0110011 // {funct7,rs2, rs1, funct3,rd,             opcode=0110011}
    `define INST_RV32I_OPCODE_FENCE   7'b0001111 // {fm, pred, succ,s1, 000, rd,             opcode=0001111}
    `define INST_RV32I_OPCODE_CSR     7'b1110011 // {csr,       rs1, funct3, rd,             opcode=1110011}

    `define INST_RV64I_OPCODE_SHIFT_W 7'b0011011  
    `define INST_RV64IM_OPCODE_REG    7'b0111011 

    `define INST_RV32M_OPCODE_REG     7'b0110011 

    /*---Branch type inst---*/
    `define INST_RV32I_BEQ         3'b000
    `define INST_RV32I_BNE         3'b001
    `define INST_RV32I_BLT         3'b100
    `define INST_RV32I_BGE         3'b101
    `define INST_RV32I_BLTU        3'b110
    `define INST_RV32I_BGEU        3'b111
    /*---Load type inst---*/
    `define INST_RV32I_LB          3'b000
    `define INST_RV32I_LH          3'b001
    `define INST_RV32I_LW          3'b010
    `define INST_RV32I_LD          3'b011
    `define INST_RV32I_LBU         3'b100
    `define INST_RV32I_LHU         3'b101    
    `define INST_RV32I_LWU         3'b110
    /*---Store type inst---*/
    `define INST_RV32I_SB          3'b000
    `define INST_RV32I_SH          3'b001
    `define INST_RV32I_SW          3'b010
    `define INST_RV32I_SD          3'b011
    /*---Imm type inst---*/
    `define INST_RV32I_ADDI        3'b000
    `define INST_RV32I_SLTI        3'b010
    `define INST_RV32I_SLTIU       3'b011
    `define INST_RV32I_XORI        3'b100
    `define INST_RV32I_ORI         3'b110
    `define INST_RV32I_ANDI        3'b111
    `define INST_RV32I_SLLI        3'b001  
    `define INST_RV32I_SRLI_SRAI   3'b101 	
    /*---Reg type inst---*/
    `define INST_RV32I_ADD_SUB     3'b000                                       
    `define INST_RV32I_SLL         3'b001
    `define INST_RV32I_SLT         3'b010
    `define INST_RV32I_SLTU        3'b011
    `define INST_RV32I_XOR         3'b100
    `define INST_RV32I_SRL_SRA     3'b101                                       
    `define INST_RV32I_OR          3'b110
    `define INST_RV32I_AND         3'b111 	
    /*---CSR type inst---*/
    `define INST_RV32I_CSRRW       3'b001
    `define INST_RV32I_CSRRS       3'b010
    `define INST_RV32I_CSRRC       3'b011
    `define INST_RV32I_CSRRWI      3'b101
    `define INST_RV32I_CSRRSI      3'b110
    `define INST_RV32I_CSRRCI      3'b111
    `define INST_RV32I_CSR_SPECIAL 3'b000
    /*---Fence type inst---*/
    `define INST_RV32I_FENCE       3'b000
    `define INST_RV32I_FENCE_I     3'b001
    /*---64I type inst---*/
    
    `define INST_RV64I_ADDW_SUBW   3'b000
    `define INST_RV64I_SLLW        3'b001
    `define INST_RV64I_SRLW_SRAW   3'b101

    `define INST_RV64I_SLLIW       3'b001  
    `define INST_RV64I_SRLIW_SRAIW 3'b101  
    /*---32M type inst---*/
    `define INST_RV32M_MUL     3'b000                                       
    `define INST_RV32M_MULH    3'b001
    `define INST_RV32M_MULHSU  3'b010
    `define INST_RV32M_MULHU   3'b011
    `define INST_RV32M_DIV     3'b100
    `define INST_RV32M_DIVU    3'b101
    `define INST_RV32M_REM     3'b110
    `define INST_RV32M_REMU    3'b111
    /*---64M type inst---*/
    `define INST_RV64M_MULW    3'b000
    `define INST_RV64M_DIVW    3'b100
    `define INST_RV64M_DIVUW   3'b101
    `define INST_RV64M_REMW    3'b110
    `define INST_RV64M_REMUW   3'b111

/*---Alu op---*/
	/*---exe_type---*/
    `define EXE_TYPE_NOP            4'b0000
    `define EXE_TYPE_BRANCH         4'b0001
    `define EXE_TYPE_COMMON         4'b0010
    `define EXE_TYPE_MUL            4'b0011
    `define EXE_TYPE_DIV            4'b0100
    `define EXE_TYPE_LOAD           4'b0101
    `define EXE_TYPE_STORE          4'b0110
    `define EXE_TYPE_LUI            4'b0111
    `define EXE_TYPE_AUIPC          4'b1000
    `define EXE_TYPE_JAL            4'b1001
    `define EXE_TYPE_JALR           4'b1010   
	/*---uop_code---*/
    `define UOP_CODE_NOP            6'd0
    `define UOP_CODE_LUI            6'd1
    `define UOP_CODE_AUIPC          6'd2
    `define UOP_CODE_JAL            6'd3
    `define UOP_CODE_JALR           6'd4

    `define UOP_CODE_BEQ            6'd5
    `define UOP_CODE_BNE            6'd6
    `define UOP_CODE_BGE            6'd7
    `define UOP_CODE_BGEU           6'd8
    `define UOP_CODE_BLT            6'd9
    `define UOP_CODE_BLTU           6'd10

    `define UOP_CODE_LB             6'd11
    `define UOP_CODE_LBU            6'd12
    `define UOP_CODE_LH             6'd13
    `define UOP_CODE_LHU            6'd14
    `define UOP_CODE_LW             6'd15

    `define UOP_CODE_SB             6'd16
    `define UOP_CODE_SH             6'd17
    `define UOP_CODE_SW             6'd18

    `define UOP_CODE_ADDI           6'd19

    `define UOP_CODE_SLTI           6'd20
    `define UOP_CODE_SLTIU          6'd21

    `define UOP_CODE_ANDI           6'd22
    `define UOP_CODE_ORI            6'd23
    `define UOP_CODE_XORI           6'd24

    `define UOP_CODE_SLLI           6'd25
    `define UOP_CODE_SRLI           6'd26
    `define UOP_CODE_SRAI           6'd27

    `define UOP_CODE_ADD            6'd28
    `define UOP_CODE_SUB            6'd29

    `define UOP_CODE_AND            6'd30
    `define UOP_CODE_OR             6'd31
    `define UOP_CODE_XOR            6'd32

    `define UOP_CODE_SLL            6'd33
    `define UOP_CODE_SRL            6'd34
    `define UOP_CODE_SRA            6'd35
    
    `define UOP_CODE_SLT            6'd36
    `define UOP_CODE_SLTU           6'd37
    
    `define UOP_CODE_MUL            6'd38
    `define UOP_CODE_MULH           6'd39
    `define UOP_CODE_MULHU          6'd40
    `define UOP_CODE_MULHSU         6'd41
    
    `define UOP_CODE_DIV            6'd42
    `define UOP_CODE_DIVU           6'd43
    `define UOP_CODE_REM            6'd44
    `define UOP_CODE_REMU           6'd45
    
    `define UOP_CODE_MULW           6'd46
    
    `define UOP_CODE_DIVW           6'd47
    `define UOP_CODE_DIVUW          6'd48
    `define UOP_CODE_REMW           6'd49
    `define UOP_CODE_REMUW          6'd50

    `define UOP_CODE_LD             6'd51
    `define UOP_CODE_SD             6'd52

    `define UOP_CODE_ADDW           6'd53
    `define UOP_CODE_SUBW           6'd54
    `define UOP_CODE_SLLW           6'd55
    `define UOP_CODE_SRLW           6'd56
    `define UOP_CODE_SRAW           6'd57
    `define UOP_CODE_SLLWI          6'd58
    `define UOP_CODE_SRLWI          6'd59
    `define UOP_CODE_SRAWI          6'd60

    `define UOP_CODE_LWU            6'd61//
    `define UOP_CODE_ADDIW          6'd62//Addition
    /*---LOAD SEL---*/	
    `define LB                     3'b001
    `define LBU                    3'b010
    `define LH                     3'b011
    `define LHU                    3'b100
    `define LW                     3'b101
    `define LWU                    3'b110
    `define LD                     3'b111

    `define WORD_LENTH             32
    `define DOUBLE_LENTH           64


    `define INST_RV32I_OPCODE_LUI     7'b0110111 // {imm[31:12],             rd,             opcode=0110111}
    `define INST_RV32I_OPCODE_AUIPC   7'b0010111 // {imm[31:12],             rd,             opcode=0010111}
    `define INST_RV32I_OPCODE_JAL     7'b1101111 // {imm[20|10:1|11|19:12],  rd,             opcode=1101111}
    `define INST_RV32I_OPCODE_JALR    7'b1100111 // {imm[11:0],  rs1, 000,   rd,             opcode=1100111}
    `define INST_RV32I_OPCODE_BRANCH  7'b1100011// {imm[12|10:5],rs2,rs1,funct3,imm[4:1|11], opcode=1100011}
    `define INST_RV32DI_OPCODE_LOAD   7'b0000011 // {imm[11:0],  rs1, funct3,rd,             opcode=0000011}
    `define INST_RV32DI_OPCODE_STORE  7'b0100011 // {imm[11:5],  rs2, rs1,funct3,imm[4:0],   opcode=0100011}
    `define INST_RV32I_OPCODE_IMM     7'b0010011 // {imm[11:0],  rs1, funct3,rd,             opcode=0010011}
    `define INST_RV32I_OPCODE_CSR     7'b1110011 // {csr,       rs1, funct3, rd,             opcode=1110011}
    `define INST_RV32I_OPCODE_FENCE   7'b0001111 // {fm, pred, succ,s1, 000, rd,             opcode=0001111}
    `define INST_RV64I_OPCODE_SHIFT_D 7'b0010011 
    `define INST_RV64I_OPCODE_LOAD    7'b0000011 
    `define INST_RV64I_OPCODE_STORE   7'b0100011  
    `define INST_RV32I_SLLI           3'b001  
    `define INST_RV32I_SRLI_SRAI      3'b101 	
